SBASAW0
February 2024
ADS1288
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Timing Requirements: 1.65V ≤ IOVDD ≤ 1.95V and 2.7V ≤ IOVDD ≤ 3.6V
5.7
Switching Characteristics: 1.65V ≤ IOVDD ≤ 1.95V and 2.7V ≤ IOVDD ≤ 3.6V
5.8
Timing Diagrams
5.9
Typical Characteristics
6
Parameter Measurement Information
6.1
Noise Performance
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Analog Input
7.3.2
PGA and Buffer
7.3.2.1
Programmable Gain Amplifier (PGA)
7.3.2.2
Buffer Operation (PGA Bypass)
7.3.3
Voltage Reference Input
7.3.4
IOVDD Power Supply
7.3.5
Modulator
7.3.5.1
Modulator Overdrive
7.3.6
Digital Filter
7.3.6.1
Sinc Filter Section
7.3.6.2
FIR Filter Section
7.3.6.3
Group Delay and Step Response
7.3.6.3.1
Linear Phase Response
7.3.6.3.2
Minimum Phase Response
7.3.6.4
HPF Stage
7.3.7
Clock Input
7.3.8
GPIO
7.4
Device Functional Modes
7.4.1
Power-Down Mode
7.4.2
Reset
7.4.3
Synchronization
7.4.3.1
Pulse-Sync Mode
7.4.3.2
Continuous-Sync Mode
7.4.4
Sample Rate Converter
7.4.5
Offset and Gain Calibration
7.4.5.1
OFFSET Register
7.4.5.2
GAIN Register
7.4.5.3
Calibration Procedure
7.5
Programming
7.5.1
Serial Interface
7.5.1.1
Chip Select (CS)
7.5.1.2
Serial Clock (SCLK)
7.5.1.3
Data Input (DIN)
7.5.1.4
Data Output (DOUT)
7.5.1.5
Data Ready (DRDY)
7.5.2
Conversion Data Format
7.5.3
Commands
7.5.3.1
Single Byte Command
7.5.3.2
WAKEUP: Wake Command
7.5.3.3
STANDBY: Software Power-Down Command
7.5.3.4
SYNC: Synchronize Command
7.5.3.5
RESET: Reset Command
7.5.3.6
Read Data Direct
7.5.3.7
RDATA: Read Conversion Data Command
7.5.3.8
RREG: Read Register Command
7.5.3.9
WREG: Write Register Command
7.5.3.10
OFSCAL: Offset Calibration Command
7.5.3.11
GANCAL: Gain Calibration Command
8
Register Map
8.1
Register Descriptions
8.1.1
ID/SYNC: Device ID, SYNC Register (Address = 00h) [Reset = xxxx0010b]
8.1.2
CONFIG0: Configuration Register 0 (Address = 01h) [Reset = 92h]
8.1.3
CONFIG1: Configuration Register 1 (Address = 02h) [Reset = 10h]
8.1.4
HPF0, HPF1: High-Pass Filter Registers (Address = 03h, 04h) [Reset = 32h, 03h]
8.1.5
OFFSET0, OFFSET1, OFFSET2: Offset Calibration Registers (Address = 05h, 06h, 07h) [Reset = 00h, 00h, 00h]
8.1.6
GAIN0, GAIN1, GAIN2: Gain Calibration Registers (Address = 08h, 09h, 0Ah) [Reset = 00h, 00h, 40h]
8.1.7
GPIO: Digital Input/Output Register (Address = 0Bh) [Reset = 000xx000b]
8.1.8
SRC0, SRC1: Sample Rate Converter Registers (Address = 0Ch, 0Dh) [Reset = 00h, 80h]
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.3
Application Curves
9.3
Power Supply Recommendations
9.3.1
Analog Power Supplies
9.3.2
Digital Power Supply
9.3.3
Grounds
9.3.4
Thermal Pad
9.4
Layout
9.4.1
Layout Guidelines
9.4.2
Layout Example
10
Device and Documentation Support
10.1
Receiving Notification of Documentation Updates
10.2
Support Resources
10.3
Trademarks
10.4
Electrostatic Discharge Caution
10.5
Glossary
11
Revision History
12
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RHB|32
MPQF130D
Thermal pad, mechanical data (Package|Pins)
RHB|32
QFND029X
Orderable Information
sbasaw0_oa
sbasaw0_pm
Data Sheet
ADS1288 32-Bit, Delta-Sigma ADC for Seismic Applications
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