SBOS671D
September 2018 – December 2022
OPA2828
,
OPA828
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Phase-Reversal Protection
7.3.2
Electrical Overstress
7.3.3
MUX Friendly Inputs
7.3.4
Overload Power Limiter
7.3.5
Noise Performance
7.3.5.1
Low Noise
7.3.6
Capacitive Load and Stability
7.3.7
Settling Time
7.3.8
Slew Rate
7.3.9
Full-Power Bandwidth
7.3.10
Small-Signal Response
7.3.11
Thermal Shutdown
7.3.12
Low Offset Voltage Drift
7.3.13
Overload Recovery
7.4
Device Functional Modes
8
Application and Implementation
8.1
Application Information
8.2
Typical Applications
8.2.1
SAR ADC Driver
8.2.1.1
Design Requirements
8.2.1.2
Detailed Design Procedure
8.2.1.3
Application Curves
8.2.2
Low-Pass Filter
8.2.2.1
Design Requirements
8.2.2.2
Detailed Design Procedure
8.2.2.3
Application Curve
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.1.1
Thermal Considerations
8.4.1.2
PowerPAD™ Design Considerations (DGN package only)
8.4.2
Layout Example
9
Device and Documentation Support
9.1
Device Support
9.1.1
Development Support
9.1.1.1
PSpice® for TI
9.1.1.2
Filter Design Tool
9.2
Documentation Support
9.2.1
Related Documentation
9.3
Receiving Notification of Documentation Updates
9.4
Support Resources
9.5
Trademarks
9.6
Electrostatic Discharge Caution
9.7
Glossary
10
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
DGN|8
MPDS046F
Thermal pad, mechanical data (Package|Pins)
DGN|8
PPTD388
Orderable Information
sbos671d_oa
sbos671d_pm
1
Features
Low input voltage noise density:
4 nV/√
Hz
at 1 kHz
Input voltage noise:
0.1 Hz to 10 Hz: 60 nV
RMS
Low input bias current:
0.1 pA (DGN)
1 pA (D)
Input offset voltage:
25 μV (DGN)
50 μV (D)
Input offset drift:
0.2 μV/°C (DGN)
0.45 μV/°C (D)
MUX-friendly inputs
Gain bandwidth: 45 MHz
Slew rate: 150 V/μs
14-bit settling time: 120 ns
Overload power limiter
Wide supply voltage range: ±4 V to ±18 V
Packages:
D Package: 8-pin SOIC
DGN Package: 8-pin HVSSOP
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