ZHCSSA6C september 2009 – june 2023 ADS1000-Q1
PRODUCTION DATA
The 16-bit output register contains the result of the last conversion in binary two’s-complement format. Because the port yields 12 bits of data, the ADS1000-Q1 outputs right-justified and sign-extended codes. This format enables averaging using a 16-bit accumulator. The output register format is shown in Figure 7-1.
Following reset or power-up, the output register is set to 00h and remains zero until the first conversion is completed. Therefore, if the ADS1000-Q1 is read just after reset or power-up, the output register reads 00h.