ZHCSQT2 March 2024 ADS127L18
ADVANCE INFORMATION
Figure 7-6 shows the block diagram of the ADC clock input circuit. The external (CLKIN pin) or internal clock oscillator signal is selected by the input clock multiplexer and is routed to all ADC channels. The clock dividers program the appropriate ADC clock frequency (fCLK) and the frame-sync port DCLK frequency (fDCLK). fCLK is divided by 2 to derive the modulator sampling clock frequency (fMOD). fCLK is also divided by 32 to drive a free-running counter for the user-based clock signal diagnostics (CLK_CNT register).
Table 7-2 shows the nominal clock frequencies corresponding to the ADC speed mode and the resulting data rates (OSR at minimum value).
SPEED MODE | CLOCK FREQUENCY (fCLK) | MAXIMUM DATA RATE (fDATA) | |
---|---|---|---|
WIDEBAND FILTER | LOW-LATENCY FILTER | ||
Max speed | 32.768MHz | 512kSPS | 1365.3 |
High speed | 25.6MHz | 400kSPS | 1066.6 |
Mid speed | 12.8MHz | 200kSPS | 533.3 |
Low speed | 3.2MHz | 50kSPS | 133.333 |