ZHCSK67B June   2017  – August 2019 ADS1287

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
    1.     Device Images
      1.      功能方框图
  4. 修订历史记录
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1 Noise Performance
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input and Multiplexer
      2. 8.3.2 Programmable Gain Amplifier (PGA)
      3. 8.3.3 Modulator
        1. 8.3.3.1 Modulator Overrange
      4. 8.3.4 Voltage Reference Inputs (REFP, REFN)
      5. 8.3.5 Digital Filter
        1. 8.3.5.1 Sinc Filter Stage
        2. 8.3.5.2 FIR Filter Stage
        3. 8.3.5.3 Group Delay and Step Response
          1. 8.3.5.3.1 Linear Phase Response
          2. 8.3.5.3.2 Minimum Phase Response
        4. 8.3.5.4 HPF Stage
      6. 8.3.6 Reset (RESET Pin and Reset Command)
      7. 8.3.7 Master Clock Input (CLK)
    4. 8.4 Device Functional Modes
      1. 8.4.1  Operational Mode
      2. 8.4.2  Chop Mode
      3. 8.4.3  Offset
      4. 8.4.4  Power-Down Mode
      5. 8.4.5  Standby Mode
      6. 8.4.6  Synchronization
        1. 8.4.6.1 Pulse-Sync Mode
        2. 8.4.6.2 Continuous-Sync Mode
      7. 8.4.7  Reading Data
        1. 8.4.7.1 Read-Data-Continuous Mode (RDATAC)
        2. 8.4.7.2 Stop-Read-Data-Continuous-Mode (SDATAC)
      8. 8.4.8  Conversion Data Format
      9. 8.4.9  Offset and Full-Scale Calibration Registers
        1. 8.4.9.1 OFC[2:0] Registers
        2. 8.4.9.2 FSC[2:0] Registers
      10. 8.4.10 Calibration Command
        1. 8.4.10.1 OFSCAL Command
        2. 8.4.10.2 GANCAL Command
      11. 8.4.11 User Calibration
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1 Chip Select (CS)
        2. 8.5.1.2 Serial Clock (SCLK)
        3. 8.5.1.3 Data Input (DIN)
        4. 8.5.1.4 Data Output (DOUT)
        5. 8.5.1.5 Serial Interface Timeout
        6. 8.5.1.6 Data Ready (DRDY)
      2. 8.5.2 Commands
        1. 8.5.2.1  WAKEUP: Wake Up Command
        2. 8.5.2.2  STANDBY: Standby Mode Command
        3. 8.5.2.3  SYNC: Synchronize ADC Conversions
        4. 8.5.2.4  RESET: Reset Command
        5. 8.5.2.5  RDATAC: Read Data Continuous Mode Command
        6. 8.5.2.6  SDATAC: Stop Read Data Continuous Mode Command
        7. 8.5.2.7  RDATA: Read Data Command
        8. 8.5.2.8  RREG: Read Register Data Command
        9. 8.5.2.9  WREG: Write Register Data Command
        10. 8.5.2.10 OFSCAL: Offset Calibration Command
        11. 8.5.2.11 GANCAL: Gain Calibration Command
    6. 8.6 Register Map
      1. 8.6.1 Register Descriptions
        1. 8.6.1.1 ID/CFG: ID, Configuration Register (address = 00h) [reset = x0h]
          1. Table 22. ID/CFG Register Field Descriptions
        2. 8.6.1.2 CONFIG0: Configuration Register 0 (address = 01h) [reset = 52h]
          1. Table 23. CONFIG0 Register Field Descriptions
        3. 8.6.1.3 CONFIG1: Configuration Register 1 (address = 02h) [reset = 08h]
          1. Table 24. CONFIG1 Register Field Descriptions
        4. 8.6.1.4 High-Pass Filter Corner Frequency (HPFx) Registers (address = 03h, 04h) [reset = 32h, 03h]
          1. Table 25. HPF0, HPF1 Registers Field Description
        5. 8.6.1.5 Offset Calibration (OFCx) Registers (address = 05h, 06h, 07h) [reset = 00h, 00h, 00h]
          1. Table 26. OFC0, OFC1, OFC2 Registers Field Description
        6. 8.6.1.6 Full-Scale Calibration (FSCx) Registers (address = 08h, 09h, 0Ah) [reset = 00h, 00h, 40h]
          1. Table 27. FSC0, FSC1, FSC2 Registers Field Description
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Geophone Application
      2. 9.2.2 Digital Interface
    3. 9.3 Initialization Set Up
  10. 10Power Supply Recommendations
    1. 10.1 Analog Power Supplies
    2. 10.2 Digital Power Supply
    3. 10.3 Power-Supply Sequence
  11. 11Layout
    1. 11.1 Layout Guidelines
  12. 12器件和文档支持
    1. 12.1 接收文档更新通知
    2. 12.2 社区资源
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 Glossary
  13. 13机械、封装和可订购信息

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • RHF|24
散热焊盘机械数据 (封装 | 引脚)
订购信息

FIR Filter Stage

The second stage of the ADS1287 digital filter is the FIR low-pass filter. Data are supplied to the FIR stage from the pre-filter, sinc stage. The FIR filter performs the final frequency response shaping. Figure 51 shows that the FIR filter is composed of four sub-stages.

ADS1287 ai_fir_sections_bas418.gifFigure 51. FIR Filter

The first two FIR stages are half-band filters with fixed decimation ratios equal to 2. The third stage decimates by a ratio equal to 4, and the fourth stage decimates by ratio equal to 2. The overall decimation ratio of the FIR stage is 32. Two coefficient sets are selectable by register bits for the third and fourth sections, one for the linear phase and one for the minimum phase response. Table 9 lists the data rates and combined decimation ratios of the sinc and FIR stage. Table 10 lists the filter coefficients that correspond to each FIR stage.

Table 9. FIR Filter Data Rates

DR[2:0] REGISTER BITS COMBINED DECIMATION RATIO (N) FIR DATA RATE (SPS)
HIGH-RESOLUTION MODE LOW-POWER MODE
000 4096 2048 62.5
001 2048 1024 125
010 1024 512 250
011 512 256 500
100 256 128 1000
101–111 Reserved Reserved Reserved

Table 10. FIR Stage Coefficients

COEFFICIENT SECTION 1 SECTION 2 SECTION 3 SECTION 4
LINEAR PHASE
SCALING =
1 / 512
LINEAR PHASE
SCALING =
1 / 8388608
SCALING = 1 / 134217728 SCALING = 1 / 134217728
LINEAR
PHASE
MINIMUM
PHASE
LINEAR
PHASE
MINIMUM
PHASE
b0 3 –10944 0 819 –132 11767
b1 0 0 0 8211 –432 133882
b2 –25 103807 –73 44880 –75 769961
b3 0 0 –874 174712 2481 2940447
b4 150 –507903 –4648 536821 6692 8262605
b5 256 0 –16147 1372637 7419 17902757
b6 150 2512192 –41280 3012996 –266 30428735
b7 0 4194304 –80934 5788605 –10663 40215494
b8 –25 2512192 –120064 9852286 –8280 39260213
b9 0 0 –118690 14957445 10620 23325925
b10 3 –507903 –18203 20301435 22008 –1757787
b11 0 224751 24569234 348 –21028126
b12 103807 580196 26260385 –34123 –21293602
b13 0 893263 24247577 –25549 –3886901
b14 –10944 891396 18356231 33460 14396783
b15 293598 9668991 61387 16314388
b16 –987253 327749 –7546 1518875
b17 –2635779 –7171917 –94192 –12979500
b18 –3860322 –10926627 –50629 –11506007
b19 –3572512 –10379094 101135 2769794
b20 –822573 –6505618 134826 12195551
b21 4669054 –1333678 –56626 6103823
b22 12153698 2972773 –220104 –6709466
b23 19911100 5006366 –56082 –9882714
b24 25779390 4566808 263758 –353347
b25 27966862 2505652 231231 8629331
b26 25779390 126331 –215231 5597927
b27 19911100 –1496514 –430178 –4389168
b28 12153698 –1933830 34715 –7594158
b29 4669054 –1410695 580424 –428064
b30 –822573 –502731 283878 6566217
b31 –3572512 245330 –588382 4024593
b32 –3860322 565174 –693209 –3679749
b33 –2635779 492084 366118 –5572954
b34 –987253 231656 1084786 332589
b35 293598 –9196 132893 5136333
b36 891396 –125456 –1300087 2351253
b37 893263 –122207 –878642 –3357202
b38 580196 –61813 1162189 –3767666
b39 224751 –4445 1741565 1087392
b40 –18203 22484 –522533 3847821
b41 –118690 22245 –2490395 919792
b42 –120064 10775 –688945 –2918303
b43 –80934 940 2811738 –2193542
b44 –41280 –2953 2425494 1493873
b45 –16147 –2599 –2338095 2595051
b46 –4648 –1052 –4511116 –79991
b47 –874 –43 641555 –2260106
b48 –73 214 6661730 –963855
b49 0 132 2950811 1482337
b50 0 33 –8538057 1480417
b51 0 0 –10537298 –586408
b52 9818477 –1497356
b53 41426374 –168417
b54 56835776 1166800
b55 41426374 644405
b56 9818477 –675082
b57 –10537298 –806095
b58 –8538057 211391
b59 2950811 740896
b60 6661730 141976
b61 641555 –527673
b62 –4511116 –327618
b63 –2338095 278227
b64 2425494 363809
b65 2811738 –70646
b66 –688945 –304819
b67 –2490395 –63159
b68 –522533 205798
b69 1741565 124363
b70 1162189 –107173
b71 –878642 –131357
b72 –1300087 31104
b73 132893 107182
b74 1084786 15644
b75 366118 –71728
b76 –693209 –36319
b77 –588382 38331
b78 283878 38783
b79 580424 –13557
b80 34715 –31453
b81 –430178 –1230
b82 –215231 20983
b83 231231 7729
b84 263758 –11463
b85 –56082 –8791
b86 –220104 4659
b87 –56626 7126
b88 134826 –732
b89 101135 –4687
b90 –50629 –976
b91 –94192 2551
b92 –7546 1339
b93 61387 –1103
b94 33460 –1085
b95 –25549 314
b96 –34123 681
b97 348 16
b98 22008 –349
b99 10620 –96
b100 –8280 144
b101 –10663 78
b102 –266 –46
b103 7419 –42
b104 6692 9
b105 2481 16
b106 –75 0
b107 –432 –4
b108 –132 0
b109 0 0

As shown in Figure 52, the FIR frequency response provides a flat pass-band response (±0.003 dB) to 0.375 fDATA. Figure 53 shows the transition band beginning from the edge of the pass band and ending at the beginning of the stop band. The stop-band response is typically –135 dB above the Nyquist frequency.

As with all oversampled systems, the pass-band response repeats at the underlying ADC sample rate. In this case, the response repeats at multiples of the modulator frequency (N·fMOD – f0 and N·fMOD + f0, where N = 1, 2, and so on, and f0 = filter pass band). These image frequencies, if not filtered and otherwise present in the signal, fold back (or alias) into the pass band causing errors. A low-pass input filter reduces aliasing. For many applications, the single-pole filter provided at the PGA output is sufficient to suppress the aliased frequencies.

ADS1287 ai_sinc_pass_bas418.gifFigure 52. FIR Filter Pass-Band Magnitude Response
ADS1287 ai_fir_trans_band_bas418.gifFigure 53. FIR Filter Transition Band Magnitude Response