ZHCSK67B June 2017 – August 2019 ADS1287
PRODUCTION DATA.
Table 15 shows that the offset calibration register is a 24-bit word composed of three 8-bit registers. The offset register is left-justified in order to align with the 32-bit conversion data. The offset value is in two's complement format with a maximum positive value of 7FFFFFh and a maximum negative value of 800000h. The register data are subtracted from the conversion data. Register data equal to 00000h perform no offset correction (default).
REGISTER | BYTE | BIT ORDER | |||||||
---|---|---|---|---|---|---|---|---|---|
OFC0 | LSB | B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 (LSB) |
OFC1 | MID | B15 | B14 | B13 | B12 | B11 | B10 | B9 | B8 |
OFC2 | MSB | B23 (MSB) | B22 | B21 | B20 | B19 | B18 | B17 | B16 |
Although the offset calibration register can accommodate values from –FS to FS (as shown in Table 16), the post-calibrated input voltage cannot exceed 106% of the nominal input range.
OFC[2:0] REGISTERS | FINAL OUTPUT CODE(1) |
---|---|
00007Fh | FFFF8100h |
000001h | FFFFFF00h |
000000h | 00000000h |
FFFFFFh | 00000100h |
FFFF7Fh | 00008100h |