ZHCSIK6C November 2017 – November 2019 ADS8166 , ADS8167 , ADS8168
PRODUCTION DATA.
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
CONVERSION CYCLE | ||||||
fCYCLE | Sampling frequency | ADS8168 | 1000 | kHz | ||
ADS8167 | 500 | |||||
ADS8166 | 250 | |||||
tCYCLE | ADC cycle-time period | ADS8168 | 1 | µs | ||
ADS8167 | 2 | |||||
ADS8166 | 4 | |||||
twh_CSZ | Pulse duration: CS high | 30 | ns | |||
twl_CSZ | Pulse duration: CS low | 30 | ns | |||
tACQ | Acquisition time | 300 | ns | |||
tqt_ACQ | Quite acquisition time | 30 | ns | |||
td_CNVCAP | Quiet aperture time | 20 | ns | |||
ASYNCHRONOUS RESET AND LOW POWER MODES | ||||||
twl_RST | Pulse duration: RST low | 100 | ns | |||
SPI-COMPATIBLE SERIAL INTERFACE | ||||||
fCLK | Serial clock frequency | 2.35 V ≤ DVDD ≤ 5.5 V,
VIH > 0.7 DVDD, VIL < 0.3 DVDD |
70 | MHz | ||
1.65 V ≤ DVDD < 2.35 V,
VIH ≥ 0.8 DVDD, VIL ≤ 0.2 DVDD |
20 | |||||
1.65 V ≤ DVDD < 2.35 V,
VIH ≥ 0.9 DVDD, VIL ≤ 0.1 DVDD |
68 | |||||
tCLK | Serial clock time period | 1/fCLK | ns | |||
tph_CK | SCLK high time | 0.45 | 0.55 | tCLK | ||
tpl_CK | SCLK low time | 0.45 | 0.55 | tCLK | ||
tph_CSCK | Setup time: CS falling to the first SCLK capture edge | 15 | ns | |||
tsu_CKDI | Setup time: SDI data valid to the SCLK capture edge | 3 | ns | |||
tht_CKDI | Hold time: SCLK capture edge to (previous) data valid on SDI | 4 | ns | |||
tht_CKCS | Delay time: last SCLK falling to CS rising | 7.5 | ns | |||
SOURCE-SYNCHRONOUS SERIAL INTERFACE | ||||||
fCLK | Serial clock frequency | 2.35 V ≤ DVDD ≤ 5.5 V, SDR (DATA_RATE = 0b) | 70 | MHz | ||
2.35 V ≤ DVDD ≤ 5.5 V, DDR (DATA_RATE = 1b) | 35 | |||||
tCLK | Serial clock time period | 1/fCLK | ns |