at TA = 25°C, VDD = 5.5 V,
external reference = 5.5 V, gain = 1 ×, and DAC outputs unloaded (unless otherwise
noted)
![AFE53902-Q1 AFE43902-Q1 Voltage Output INL vs Digital Input Code GUID-20230126-SS0I-QLNN-DBKC-JJHPPRPC6XH9-low.svg](/ods/images/SBASAC2/GUID-20230126-SS0I-QLNN-DBKC-JJHPPRPC6XH9-low.svg)
Internal reference, gain = 4 × |
Figure 6-4 Voltage Output INL vs Digital Input Code
Figure 6-6 Voltage Output INL vs Temperature![AFE53902-Q1 AFE43902-Q1 Voltage Output DNL vs Digital Input Code GUID-20230126-SS0I-1DQ8-4XFN-RLWRFCTH7F7Z-low.svg](/ods/images/SBASAC2/GUID-20230126-SS0I-1DQ8-4XFN-RLWRFCTH7F7Z-low.svg)
Internal reference, gain = 4 × |
Figure 6-8 Voltage Output DNL vs Digital Input Code
Figure 6-10 Voltage Output DNL vs Temperature![AFE53902-Q1 AFE43902-Q1 Voltage Output TUE vs Digital Input Code GUID-20230126-SS0I-L3HQ-DS2S-S0F43BKXPK1L-low.svg](/ods/images/SBASAC2/GUID-20230126-SS0I-L3HQ-DS2S-S0F43BKXPK1L-low.svg)
Internal reference, gain = 4 × |
Figure 6-12 Voltage Output TUE vs Digital Input Code
Figure 6-14 Voltage Output TUE vs Temperature
Figure 6-16 Voltage Output Offset Error vs Temperature
Figure 6-18 Voltage Output vs Load Current
Figure 6-20 Voltage Output Code-to-Code Glitch - Rising Edge![AFE53902-Q1 AFE43902-Q1 Voltage Output Setting Time - Rising Edge GUID-20220410-SS0I-P6RZ-WCS0-TH4H7GDGR4GT-low.svg](/ods/images/SBASAC2/GUID-20220410-SS0I-P6RZ-WCS0-TH4H7GDGR4GT-low.svg)
Zero
scale to full scale swing |
Figure 6-22 Voltage Output Setting Time - Rising Edge![AFE53902-Q1 AFE43902-Q1 Voltage Output Power-On Glitch GUID-20220410-SS0I-HWHM-QTB2-HCZF9CZPB39X-low.svg](/ods/images/SBASAC2/GUID-20220410-SS0I-HWHM-QTB2-HCZF9CZPB39X-low.svg)
DAC
in Hi-Z power-down mode |
Figure 6-24 Voltage Output Power-On Glitch![AFE53902-Q1 AFE43902-Q1 Voltage Output Noise Density GUID-20220410-SS0I-CG68-XTL7-MDGLNLDQMQKZ-low.svg](/ods/images/SBASAC2/GUID-20220410-SS0I-CG68-XTL7-MDGLNLDQMQKZ-low.svg)
Internal reference, gain = 4 × |
Figure 6-26 Voltage Output Noise Density![AFE53902-Q1 AFE43902-Q1 Voltage Output Flicker Noise GUID-20220410-SS0I-9PTT-1N7B-NSSN0MRDPJ8Z-low.svg](/ods/images/SBASAC2/GUID-20220410-SS0I-9PTT-1N7B-NSSN0MRDPJ8Z-low.svg)
Internal reference, gain = 4x, f = 0.1 Hz to 10
Hz |
Figure 6-28 Voltage Output Flicker Noise
Figure 6-5 Voltage Output INL vs Digital Input Code
Figure 6-7 Voltage Output INL vs Supply Voltage
Figure 6-9 Voltage Output DNL vs Digital Input Code
Figure 6-11 Voltage Output DNL vs Supply Voltage
Figure 6-13 Voltage Output TUE vs Digital Input Code
Figure 6-15 Voltage Output TUE vs Supply Voltage
Figure 6-17 Voltage Output Gain Error vs Temperature
Figure 6-19 Voltage Output AC PSRR vs Frequency
Figure 6-21 Voltage Output Code-to-Code Glitch - Falling Edge![AFE53902-Q1 AFE43902-Q1 Voltage Output Setting Time - Falling Edge GUID-20220410-SS0I-9TH4-GTX4-BT0DZTK5H5G5-low.svg](/ods/images/SBASAC2/GUID-20220410-SS0I-9TH4-GTX4-BT0DZTK5H5G5-low.svg)
Full
scale to zero scale swing |
Figure 6-23 Voltage Output Setting Time - Falling Edge
Figure 6-25 Voltage Output Power-Off Glitch
Figure 6-27 Voltage Output Noise Density
Figure 6-29 Voltage Output Flicker Noise