ZHCSL81A May   2020  – June 2021 INA229-Q1

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements (SPI)
    7. 6.7 Timing Diagram
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Versatile High Voltage Measurement Capability
      2. 7.3.2 Internal Measurement and Calculation Engine
      3. 7.3.3 Low Bias Current
      4. 7.3.4 High-Precision Delta-Sigma ADC
        1. 7.3.4.1 Low Latency Digital Filter
        2. 7.3.4.2 Flexible Conversion Times and Averaging
      5. 7.3.5 Shunt Resistor Drift Compensation
      6. 7.3.6 Integrated Precision Oscillator
      7. 7.3.7 Multi-Alert Monitoring and Fault Detection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Power-On Reset
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
        1. 7.5.1.1 SPI Frame
    6. 7.6 Register Maps
      1. 7.6.1 INA229-Q1 Registers
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Device Measurement Range and Resolution
      2. 8.1.2 Current , Power, Energy, and Charge Calculations
      3. 8.1.3 ADC Output Data Rate and Noise Performance
      4. 8.1.4 Input Filtering Considerations
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Select the Shunt Resistor
        2. 8.2.2.2 Configure the Device
        3. 8.2.2.3 Program the Shunt Calibration Register
        4. 8.2.2.4 Set Desired Fault Thresholds
        5. 8.2.2.5 Calculate Returned Values
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 接收文档更新通知
    2. 11.2 支持资源
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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Serial Interface

The primary communication between the INA229-Q1 and the external MCU is through the SPI bus, which provides full-duplex communications in a main-secondary configuration. The external MCU is always the primary or main SPI device, sending command requests on the MOSI pin, and receiving device responses on the MISO pin. The INA229-Q1 is always an SPI secondary device, receiving command requests and sending responses (status, measured values) to the external MCU over the MISO pin.

  • SPI is a 4-pin interface with pins as:
    • CS - SPI Chip Select (input)
    • SCLK - SPI Clock (input)
    • MOSI - SPI Secondary In / Main Out data (input)
    • MISO - SPI Secondary Out / Main In data (tri-state output)
  • The SPI frame size is variable in length depending on the INA229-Q1 register accessed through the SPI interface as following:
    • Main to Secondary (MOSI): 6 bits for register Address; 1 bit low; 1 R/W bit (read / not write); variable length of low bits depending on the INA229-Q1 register length.
    • Secondary to Main (MISO): 8 bits low; variable length of bits depending on the INA229-Q1 register length.
  • SPI bit-speed up to 10 Mbit/s
  • Both Main commands and INA229-Q1 data are shifted MSB first, LSB last
  • The data on the MOSI line is sampled on the falling edge of SCLK
  • The data on the MISO line is shifted out on the rising edge of SCLK

The SPI communication starts with the CS falling edge, and ends with CS rising edge. The CS high level keeps secondary SPI interface in an idle state, and MISO output is tri-stated.

Since the MISO output is push-pull it is ideal to have the INA229-Q1 supply at the same voltage as the primary device I/O supply. If different supply voltages are used, level translation is recommended.