ZHCSIZ5E
October 2018 – June 2021
IWR6443
,
IWR6843
PRODUCTION DATA
1
特性
2
应用
3
说明
4
功能方框图
5
Revision History
6
Device Comparison
6.1
Related Products
7
Terminal Configuration and Functions
7.1
Pin Diagram
7.2
Signal Descriptions
7.2.1
Signal Descriptions - Digital
7.2.2
Signal Descriptions - Analog
7.3
Pin Attributes
8
Specifications
8.1
Absolute Maximum Ratings
8.2
ESD Ratings
8.3
Power-On Hours (POH)
8.4
Recommended Operating Conditions
8.5
Power Supply Specifications
8.6
Power Consumption Summary
8.7
RF Specification
8.8
CPU Specifications
8.9
Thermal Resistance Characteristics for FCBGA Package [ABL0161]
8.10
Timing and Switching Characteristics
8.10.1
Power Supply Sequencing and Reset Timing
8.10.2
Input Clocks and Oscillators
8.10.2.1
Clock Specifications
8.10.3
Multibuffered / Standard Serial Peripheral Interface (MibSPI)
8.10.3.1
Peripheral Description
8.10.3.2
MibSPI Transmit and Receive RAM Organization
8.10.3.2.1
SPI Timing Conditions
8.10.3.2.2
SPI Master Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input) (1) (1) (1)
8.10.3.2.3
SPI Master Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input) (1) (1) (1)
8.10.3.3
SPI Slave Mode I/O Timings
8.10.3.3.1
SPI Slave Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output) (1) (1) (1)
8.10.3.4
Typical Interface Protocol Diagram (Slave Mode)
8.10.4
LVDS Interface Configuration
8.10.4.1
LVDS Interface Timings
8.10.5
General-Purpose Input/Output
8.10.5.1
Switching Characteristics for Output Timing versus Load Capacitance (CL) (1) (1)
8.10.6
Controller Area Network - Flexible Data-rate (CAN-FD)
8.10.6.1
Dynamic Characteristics for the CANx TX and RX Pins
8.10.7
Serial Communication Interface (SCI)
8.10.7.1
SCI Timing Requirements
8.10.8
Inter-Integrated Circuit Interface (I2C)
8.10.8.1
I2C Timing Requirements (1)
8.10.9
Quad Serial Peripheral Interface (QSPI)
8.10.9.1
QSPI Timing Conditions
8.10.9.2
Timing Requirements for QSPI Input (Read) Timings (1) (1)
8.10.9.3
QSPI Switching Characteristics
8.10.10
ETM Trace Interface
8.10.10.1
ETMTRACE Timing Conditions
8.10.10.2
ETM TRACE Switching Characteristics
8.10.11
Data Modification Module (DMM)
8.10.11.1
DMM Timing Requirements
8.10.12
JTAG Interface
8.10.12.1
JTAG Timing Conditions
8.10.12.2
Timing Requirements for IEEE 1149.1 JTAG
8.10.12.3
Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Subsystems
9.3.1
RF and Analog Subsystem
9.3.1.1
Clock Subsystem
9.3.1.2
Transmit Subsystem
9.3.1.3
Receive Subsystem
9.3.2
Processor Subsystem
9.3.3
Host Interface
9.3.4
Main Subsystem Cortex-R4F
9.3.5
DSP Subsystem
9.3.6
Hardware Accelerator
9.4
Other Subsystems
9.4.1
ADC Channels (Service) for User Application
9.4.1.1
GP-ADC Parameter
10
Monitoring and Diagnostics
10.1
Monitoring and Diagnostic Mechanisms
10.1.1
Error Signaling Module
11
Applications, Implementation, and Layout
11.1
Application Information
11.2
Reference Schematic
12
Device and Documentation Support
12.1
Device Nomenclature
12.2
Tools and Software
12.3
Documentation Support
12.4
支持资源
12.5
Trademarks
12.6
Electrostatic Discharge Caution
12.7
术语表
13
Mechanical, Packaging, and Orderable Information
13.1
Packaging Information
13.2
Tray Information for ABL, 10.4 × 10.4 mm
8.2
ESD Ratings
VALUE
UNIT
V
(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
±2000
V
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002
(2)
(3)
±500
(1)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process
(2)
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process
(3)
Corner pins are rated as ±750 V
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